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Ceis 2 - VC-ADSR

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Ceis 2 - VC-ADSR

The Instruō cèis[2] is a fully analogue voltage controlled ADSR envelope generator. The ADSR function generator is the model pioneered by the East-coast mindset and is extensively used in subtractive synthesis patches. The cèis[2] gives the ability to externally control the attack, decay, sustain, and release stages of the envelope while also emitting trigger and gate signals for each segment, offering maximum versatility from a classic tool. 

This version[2] revision brings additional flexibility and control through a completely redesigned logic extraction circuit for the segment gates, envelope re-trigger input, and a precision throughput for voltage controlled slew limiter capabilities.

The Instruō cèis[2] is a fully analogue voltage controlled ADSR envelope generator. The ADSR function generator is the model pioneered by the East-coast mindset and is extensively used in subtractive synthesis patches. The cèis[2] gives the ability to externally control the attack, decay, sustain, and release stages of the envelope while also emitting trigger and gate signals for each segment, offering maximum versatility from a classic tool. 

This version[2] revision brings additional flexibility and control through a completely redesigned logic extraction circuit for the segment gates, envelope re-trigger input, and a precision throughput for voltage controlled slew limiter capabilities.

$80.15

Original: $229.00

-65%
Ceis 2 - VC-ADSR

$229.00

$80.15

Description

The Instruō cèis[2] is a fully analogue voltage controlled ADSR envelope generator. The ADSR function generator is the model pioneered by the East-coast mindset and is extensively used in subtractive synthesis patches. The cèis[2] gives the ability to externally control the attack, decay, sustain, and release stages of the envelope while also emitting trigger and gate signals for each segment, offering maximum versatility from a classic tool. 

This version[2] revision brings additional flexibility and control through a completely redesigned logic extraction circuit for the segment gates, envelope re-trigger input, and a precision throughput for voltage controlled slew limiter capabilities.